There are many different, but generally related, methods and devices used for recovering a clock signal from random data bits received by a receiver. Such devices include a local oscillator, having a phase and/or frequency that is adjusted to the phase and/or frequency of the received data. A phase error signal indicative of the deviation between the received data bits and an output of the local oscillator is derived. The phase error signal is filtered or averaged to derive a control signal for the phase of a clock signal derived from the local oscillator. Thereby, the local clock signal is synchronized to the phase of the incoming data bit stream.
A typical prior art device for deriving the phase error indication employs so called early-late gate circuitry. In such circuitry, a phase error signal for each received data bit is derived by dividing each bit into two time sequential halves, the occurrence times of which are controlled by the phase of the clock signal. The relative energy in the two halves resulting from each bit is determined by integrating the first and second halves of each bit. The absolute value of the integrated halves are compared to derive the control signal for the local oscillator. In response to the two halves having the same energy, no phase change occurs in the local oscillator. If, however, the local oscillator and the received data stream do not have the same phase, one of the halves of the data bits has a transition therein. Thereby, the integral over the bit half having the transition therein is smaller than the other bit half, resulting in the derivation of a finite, non-zero error signal. The phase error signal either advances or retards the local clock until data transitions of the received data bits occur at the boundary between the early and late halves.
A primary disadvantage of the typical early-late gate arrangement in achieving synchronization between a local oscillator clock source and the received data stream concerns the manner in which the phase error signal is derived. The maximum phase error occurs when the local oscillator is phase displaced by one quarter of a bit from the received bit. The phase error signal has a zero value in response to the phase of the received bit and the local oscillator being in phase, as well as one half bit out of phase. In a theoretical, noiseless system, it is possible for the local oscillator to become synchronized to the received bit stream at a position such that the local oscillator is phase displaced by one half a bit from the bits of the received data stream. In actuality, synchronization in this manner does not occur because of noise superimposed by the transmission medium on the received bits. However, the non-monotonic nature of the relationship between phase displacement of the local oscillator to the received data stream bits versus the amplitude of the phase error signal can cause a substantial time delay in achieving synchronization between the clock signal and the received data stream.
The typical prior art early-late gate systems have employed analog components, although some systems have employed more reliable digital techniques. One such digital technique is disclosed in Stepp et al, U.S. Pat. No. 4,535,461. In the Stepp et al patent, each bit of a received random data stream is divided into several samples of the amplitude of the bit. Each sample causes a binary sub-bit to be derived so that the binary value of a sub-bit depends on the amplitude of the corresponding sample; in the specific example of the Stepp et al patent, each received data bit is divided into sixteen sub-bits. The number of binary one bits in the first eight sub-bits is compared with the number of binary one bits in last eight sub-bits of each received data bit. In response to the number of binary one bits in the two halves being equal, the frequency of pulses derived from a local clock source, which derives an output to control the sampling times of each received data bit to derive the sub-bits, is set to a median, predetermined value. In response to the number of binary ones in the first half of each received data bit exceeding the number of binary ones in the second half of each received data bit, the frequency of the local oscillator is incremented to a second predetermined frequency and there is a predetermined fixed advance in the sampling times of the following received data bits. In response to the number of binary ones in the second half of each received data bit exceeding the number of binary ones in the first half of each received data bit, the local oscillator frequency is decremented from the median value, to a third predetermined value and there is a predetermined fixed delay in the sampling times of the following received data bits. Control of the local oscillator is preferably attained by averaging a comparator output indicative of the relative number of binary one bits over several received bits.
To determine the value of the received binary bit, the binary value of the sixteen sub-bits is compared with a threshold value.
The prior art Stepp et al system, in addition to being somewhat complex, reacts relatively slowly to control the clock synchronization. The slow response time is due to the need to filter the output of the comparator, as well as the relatively low resolution of the comparator. In the Stepp et al device the same control is provided for the local oscillator regardless of the phase displacement between the clock and the received data bits. For example, the phase control signal has the same value for a phase displacement between the local oscillator and the received data bit of seven-sixteenths of a received data bit as for a phase displacement of one-sixteenth of a received data bit.
A further object of the invention is to provide a new and improved relatively high speed apparatus for synchronizing a local oscillator to bits of a received data stream.
It is frequently desirable, particularly in noisy transmission links, to provide signals to different types of bit decoders. For example, if the transmission link has a relatively low noise level, whereby the received signal has a high signal-to-noise ratio, a bit to character decoder responsive to hard bit decisions is adequate. In other, noisy transmission links wherein the received signal has a low signal-to-noise ratio, frequently resulting in multiple transitions within a bit, a so-called erasure bit is derived and combined with a hard decision bit in a bit to a character decoder of another type. In transmission links having greater noise, resulting in received data bits having even lower signal-to-noise ratios, a hard decision bit is combined with plural "quality" bits which are supplied to still another type of decoder. Prior art systems have required considerable hardware or computer requirements to derive the erasure and quality bits.
An object of the invention is to provide a new and improved apparatus for and method of deriving indications of the noise level of a binary data bit received by a receiver over transmission links having varying noise characteristics.